Cerebras published a technical walkthrough this week of the question it says it gets asked most often: how do you actually run a trillion-parameter model on wafer-scale hardware? The answer, worked through with the open-weight model Kimi K3, is that you don't run it on a chip. You run it on 59 of them — and you arrange the deployment so the weights never move again.
The constraint is memory, not math
A single WSE-3T wafer carries 44 GB of on-chip SRAM. Kimi K3 has roughly 3 trillion parameters; held at 4 bits each — the quantization the Hugging Face release uses — that is about 1.5 terabytes of weights alone. A frontier model does not fit on a wafer, or on any plausible single package.
Cerebras' post breaks the model into its 93 layers, which works out to roughly 16 GB per layer. That single number decides the whole floor plan, because 16 GB is comfortably smaller than 44 GB. Layers are never split across chips: each wafer holds whole layers, with room left over.
What that leftover room is for depends on the layer type, and this is the part worth reading twice. Dense, full-attention layers have to store keys and values for every token of every request in flight, so each one gets a wafer to itself: 16 GB of weights, and the remaining 28 GB handed to the KV cache. Linear-attention layers don't work that way — they carry a small fixed-size state per request regardless of context length — so they need no KV cache at all and fit two to a wafer. Kimi K3 has 69 linear layers and 24 dense ones, which gives 35 wafers for the linear stack plus 24 for the dense layers: 59 in total.
The architecture is doing as much work here as the hardware. A model built mostly from linear-attention layers is what makes a multi-wafer layout this clean, because most of the model stops competing with request state for memory.
Only activations cross the wire
Once the compiler has mapped layers onto wafers, the runtime becomes an assembly line. Wafer 1 runs layers 1–2 and hands its activations to wafer 2, which runs layers 3–4, and so on until the last stage emits a token. The hops go over RDMA over Ethernet at roughly 2 microseconds each. Weights stay where they were placed; the only traffic is intermediate results.
The obvious objection — doesn't a pipeline of 59 stages mean every wafer sits idle waiting its turn, an effective batch size of one? — is the one Cerebras spends the most words dismantling. The pipeline stays full of different requests: while stage 3 works on a token for request A, stage 2 works on one for request B and stage 1 on request C. Each stage can also take a micro-batch rather than a single request, so requests in flight scale with stages times micro-batch size. Smaller micro-batches favour latency, larger ones favour total throughput.
That is how the company gets to its headline claim of 1,000–2,000+ tokens per second on a multi-trillion-parameter model.
Where the ceiling actually is
Concurrency, not compute, is the binding limit. Every in-flight request needs its own KV cache on every dense-layer wafer, so the 28 GB left over on each of those 24 wafers sets the maximum number of simultaneous requests. Cerebras works the division in the post rather than quoting a single number, and the assumptions matter: an average request of 256k tokens and an 8-bit KV cache. Longer contexts or a wider cache shrink concurrency proportionally.
The second limit is structural, and it was the sharpest point raised in discussion of the post. A GPU cluster degrades: lose a node and the job continues more slowly, or a replica absorbs the traffic. Here the model is the rack. One bad wafer stops the assembly line, and a 59-wafer pipeline has 59 chances to meet a bad wafer. Cerebras' post does not address redundancy or failover; it is a layout document, not an availability one.
The company closes with a warning about how such systems get compared. Concurrency and batch size, it argues, don't tell you much about efficiency; the meaningful figure is tokens per second per megawatt, measured at the same output generation speed, so that throughput claims can't be bought with latency.
Why it matters
Cerebras has spent the year arguing that inference economics, not training runs, is where wafer-scale wins — the CS-4 rack-scale system in August, and its chief executive's predictions since. This post is the least promotional thing it has published in that campaign: a floor plan with the arithmetic shown, including the places where the arithmetic is tight. For anyone serving open-weight models, it is also a reminder that a 3-trillion-parameter model is no longer a research object. It is a deployment shape, and the shape is 59 chips in a line.
